The present invention relates to a digital computer system, and more particularly, to an address translation method and an apparatus therefor capable of efficiently using a main storage.
Virtual memory systems are widely and commonly used for computer systems to realize superior function, performance and facility. In a virtual memory system, an address of a main storage indicated by a program is a logical address which is subjected to address translation by address translation facilities of the computer system. A real address obtained through address translation is used in accessing the main storage. Various address translation methods such as segmentation, paging and the like are employed, and a suitable one for a particular computer system is selected.
The concept of a virtual memory system and its particular example are described in various texts and documents.
Of various address translation methods with virtual memories, there is known a method wherein the address translation size can be changed with a program by including in the program status word (PSW) thereof a bit indicative of the address translation size, as disclosed in JP-A-62-73347.
An example of address translation in a supercomputer is disclosed in "HITAC Supercomputer S-820 Functional Description" pp. 19 to 21, July 1986 presented by the same assignee. In this address translation method, there are provided a segment relocation register for address translation in units of segment, and a page relocation register for address translation in units of page. Which size is to be used in address translation is determined by a bit, indicative of the address translation size, of a logical address within the segment relocation register. Namely, if the bit is 0, an entry of the segment relocation register is designated by the segment index field of a logical address, to perform address translation in units of segment. If the bit is 1, an entry of the page relocation register is designated by a combined portion of the segment and page index fields of a logical address, to perform address translation in units of page.
An analysis by the present inventors of the conventional address translation in a computer system disclosed in JP-A-62-73347 showed that the size (which is often called as segment size or page size, and 4 KB, 1 MB or the like has been adopted) of address translation is fixed in the computer system. Even if a plurality of sizes could be used selectively, the size is fixed for each program.
Consider the main storage control method for such a computer system. For example, in a scientific and mathematical use oriented computer system, address translation for a system control task is carried out in units of relatively small memory capacity, whereas address translation for scientific and mathematical use handling considerably large matrix data is carried out in units of relatively large memory capacity. Thus, not only the main storage can be efficiently used, but also the amount of translation tables required for address translation can be reduced (because of reverse proportion of the translation table amount relative to the address translation size), resulting in a simplicity of the main storage control. However, such appropriate main storage control cannot be realized by a conventional method wherein the address translation size cannot be cahnged dynamically within one program.
Further, in address translation of the computer system described in HITAC Supercomputer S-820 Functional Description, two types of sizes, i.e., segment and page, can be used selectively for each program. However, if it is intended to realize that the address size can be used selectively for a desired logical address, a page relocation register which covers the entirety of the logical address space must be provided so that a problem of extremely increasing the hardware quantity occurs. In the HITAC Supercomputer S-820, the logical addresses smaller than 16 MB are translated in units of page, whereas the logical addresses equal to or larger than 16 MB are translated in units of segment. Thus, the address translation size is ambiguously determined in accordance with the logical address, to thereby avoid an increase of hardware quantity. However, there arises a problem of the restriction that the translation size is selectively used on both sides of a predetermined fixed logical address.